Processor has three main parts: ALU, control unit and system clock.
A limited amount of data are stored inside the processor while they are worked on by the instructions of the processor. Data is stored inside the processor in registers. Key registers include:
Instructions are fetched from memory and executed in the CPU. These actions are arranged in a cycle that is controlled by the system clock. The system clock provides a regular pulse at a certain frequency (the higher the frequency the faster the CPU). Twenty years ago clock cycles were measured in MegaHertz (MHz) (e.g. 2 MHz), ten years ago in tens of MHz (e.g. 90MHz), now they are measured in thousands of Hz (e.g. 2000MHz or 2GHz) - as predicted by Gordon Moore.
Data moves around a computer, to and from the CPU and other devices such as network, sound and graphics cards, on the pulse of the system clock. There are three main steps to this:
Most CPUs do more than one thing inside each clock cycle, for example performing a fetch of the next instruction while the current instruction is being executed. As well as getting faster as transistor size falls CPUs get smarter by design as engineers find ways to do more than one thing at a time.
Interrupts are a key mechanism of a computer. Computers consist of many items of hardware, each of which has to be 'serviced' in some way, typically by reading data from it or sending data to it. A mouse or keyboard, for example, may lay unused while a computer is on but as soon as they are touched the computer must acknowledge them and act on input from them, e.g. record the key pressed or move the mouse pointer across the screen. Devices like this are scanned or monitored within the clock cycles of the CPU and, if one of them requires action, an interrupt is generated and the CPU jumps to a piece of code called an interrupt handler. (In high level object-oriented terms this is an event.)
Types of interrupt include:
The CPU includes an interrupt register that records whether an interrupt has occurred and requires the CPU to take action according to what sort of request has occurred - mouse movement or click, keyboard press, screen refresh, sound card output, joy stick movement, and so on. Each interrupt type is assigned to a bit in the register, rather like the status register.
Interrupts are assigned priorities according to their importance so that an interrupt of lower priority cannot interrupt one of higher priority.
When an interrupt occurs the current instruction should be completed and then the following will occur:
Interrupt handlers are likely to be stored in adjacent locations in a reserved part of memory. The mechanism to set the PC to the appropriate address will be a base-offset mechanism such as indexed or indexed indirect addressing. This is also known as a vectored interrupt mechanism, where the offset or vector is added to the base address to produce the exact address of the handler.
Most computers still follow a design developed by John von Neumann in the 1940s, whereby instructions and data are transmitted between memory and processor along data and address buses. The address bus provides a one-way path from the processor to memory (and memory-mapped devices) so that locations can be identified or addressed. The data bus provides a two-way path for data to flow to and fro between memory and CPU.
The width of the data bus determines how much data can be transferred in one go (32 bits is now standard, 64 bits just emerging, larger values in mainframe and super computers). The address bus determines how much memory a CPU can reach: 16 bits provides 2^16=65,536 locations, 32 bits provides 2^32 = 4Gbytes, 64 bits provides 2^64 bytes (a lot!). Note that an increase of 1 bit in the width of the address bus leads to a doubling of addressable memory; a doubling of bits from 8 to 16 leads to an increase from 2^8 to 2^16, not an arithmetic doubling from 256 to 512.
If it takes, say, one clock cycle for instructions and data to travel to and from the CPU and three clock cycles for a typical instruction to be executed the CPU could be seen as a 'bottleneck', slowing down the overall speed of the computer. Various techniques have been devised to improve this situation e.g. multiple processors, performing a fetch at the same time as execution, cache memory to store recently used data and instructions, 'pipelining' or by predicting what is most likely to come next and making sure it is available when required.